3.3.4.29. USB DWC3 — Processor SDK Linux Documentation
Synopsys Expands Multi-Die Solution Leadership with Industry's Lowest Latency Die-to-Die Controller IP
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
DWTB: How to Connect Your DesignWare USB 2.0 nanoPHY to Your DesignWare USB 2.0 OTG Controller
Synopsys readies 10Gbit/s USB 3.1 IP and verification support
The USB 3.0 functional layer
Synopsys Demonstrates USB 3.2 with Throughput Speeds Up to 20 Gbps | TechPowerUp Forums
USB 2.0 Host Controller IP Core
Synopsys' DesignWare IP for USB and PCI Express. | IT Eco Map & News Navigator
USB 3.1 IP | DesignWare IP | Synopsys
Popular USB DWC3 Linux Driver Likely To "Never Be Finished" With Continued Adaptations - Phoronix
USB IP University | Interface IP | DesignWare IP | Synopsys
Understanding USB 3.2 and Type-C - Tech Design Forum Techniques
USB 2.0 Device Controller
I want to use USB Type C (and I want it now) - SemiWiki
DWTB: How to Connect Your DesignWare USB 2.0 nanoPHY to Your DesignWare USB 2.0 OTG Controller
USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it? - 摩斯电码 - 博客园
USB - Kobol Wiki
Delivering on the Promise of Guaranteed Isochronous Traffic in USB 3.1 — Synopsys Technical Article | ChipEstimate.com
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Upgrade Your SoC Design With USB4 IP
GitHub - stm32-rs/synopsys-usb-otg: usb-device implementation for Synopsys USB OTG IP cores
Synopsys readies 10Gbit/s USB 3.1 IP and verification support
USB IP | Interface IP | DesignWare IP| Synopsys
